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Features
* Low Pin Count (LPC) BIOS Device * Functions as Firmware Hub for Intel 810, 810E, 820, 840 Chipsets * 8M or 4M Bits of Flash Memory for Platform Code/Data Storage
- Uniform, 64-Kbyte Memory Sectors - Available in 8M Bits (AT49LW080) and 4M Bits (AT49LW040) - Automated Byte-program and Sector-erase Operations Two Configurable Interfaces - Firmware Hub (FWH) Interface for In-System Operation - Address/Address Multiplexed (A/A Mux) Interface for Programming during Manufacturing Firmware Hub Hardware Interface Mode - 5-signal Communication Interface Supporting x8 Reads and Writes - Read and Write Protection for Each Sector Using Software-controlled Registers - Two Hardware Write-protect Pins: One for the Top Boot Sector, One for All Other Sectors - Five General-purpose Inputs, GPIs, for Platform Design Flexibility - Operates with 33 MHz PCI Clock and 3.3V I/O Address/Address Multiplexed (A/A Mux) Interface - 11-pin Multiplexed Address and 8-pin Data Interface - Supports Fast On-board or Out-of-system Programming Power Supply Specifications - VCC: 3.3V 0.3V - VPP: 3.3V and 12V for Fast Programming Industry-standard Packages - (40-lead TSOP or 32-lead PLCC)
*
*
8-megabit and 4-megabit Firmware Hub Flash Memory AT49LW080 AT49LW040
* * *
Description
The AT49LW080 and the AT49LW040 are Flash memory devices designed to be compatible with the Intel 82802AC and the Intel 82802AB Firmware Hub (FWH) devices for PC-Bios Application. A feature of the AT49LW080/040 is the nonvolatile memory core. The high-performance memory is arranged in eight (AT49LW040) or sixteen (AT49LW080) 64-Kbyte sectors (see page 13).
Pin Configurations
PLCC
FGPI2 [A8] FGPI3 [A9] RST [RST] VPP [VPP] VCC [VCC] CLK [R/C] FGPI4 [A10]
(NC) NC [IC (VIH)] IC (VIL) [NC] NC [NC] NC [NC] NC [NC] NC [A10] FGPI4 [NC] NC [R/C] CLK [VCC] VCC [VPP] VPP [RST] RST [NC] NC [NC] NC [A9] FGPI3 [A8] FGPI2 [A7] FGPI1 [A6] FGPI0 [A5] WP [A4] TBL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
TSOP
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GNDa [GNDa] VCCa [VCCa] FWH4 [WE] INIT [OE] RFU [RY/BY] RFU [I/O7] RFU [I/O6] RFU [I/O5] RFU [I/O4] VCC [VCC] GND [GND] GND [GND] FWH3 [I/O3] FWH2 [I/O2] FWH1 [I/O1] FWH0 [I/O0] ID0 [A0] ID1 [A1] ID2 [A2] ID3 [A3]
[ ] Designates A/A Mux Mode
[I/O1] FWH1 [I/O2] FWH2 [GND] GND [I/O3] FWH3 [I/O4] RFU [I/O5] RFU [I/O6] RFU
14 15 16 17 18 19 20
[A7] FGPI1 [A6] FGPI0 [A5] WP [A4] TBL [A3] ID3 [A2] ID2 [A1] ID1 [A0] ID0 [I/O0] FWH0
5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
IC (VIL) [IC(VIH)] GNDa [GNDa] VCCa [VCCa] GND [GND] VCC [VCC] INIT [OE] FWH4 [WE] RFU [RY/BY] RFU [I/O7]
[ ] Designates A/A Mux Mode
Rev. 1966C-FLASH-03/02
1
The AT49LW080/040 supports two hardware interfaces: Firmware Hub (FWH) for insystem operation and Address/Address Multiplexed (A/A Mux) for programming during manufacturing. The IC (Interface Configuration) pin of the device provides the control between the interfaces. The interface mode needs to be selected prior to power-up or before return from reset (RST or INIT low to high transition). An internal Command User Interface (CUI) serves as the control center between the two device interfaces (FWH and A/A Mux) and internal operation of the nonvolatile memory. A valid command sequence written to the CUI initiates device automation. Specifically designed for 3V systems, the AT49LW080/040 supports read operations at 3.3V and sector erase and program operations at 3.3V and 12V VPP . The 12V V PP option renders the fastest program performance which will increase factory throughput, but is not recommended for standard in-system FWH operation in the platform. With the 3.3V VPP option, VCC and VPP should be tied together for a simple, low-power 3V design. In addition to the voltage flexibility, the dedicated VPP pin gives complete data protection when VPP V PPLK. Internal V PP detection circuitry automatically configures the device for sector erase and program operations. Note that, while current for 12V programming will be drawn from VPP, 3.3V programming board solutions should design such that VPP draws from the same supply as VCC, and should assume that full programming current may be drawn from either pin.
Firmware Hub Interface
The Firmware Hub (FWH) interface is designed to work with the I/O Controller Hub (ICH) during platform operation. The FWH interface consists primarily of a five-signal communication interface used to control the operation of the device in a system environment. The buffers for this interface are PCI compliant. To ensure the effective delivery of security and manageability features, the FWH interface is the only way to get access to the full feature set of the device. The FWH interface is equipped to operate at 33 MHz, synchronous with the PCI bus.
Address/Address Multiplexed Interface
The A/A Mux interface is designed as a programming interface for OEMs to use during motherboard manufacturing or component pre-programming. The A/A Mux refers to the multiplexed row and column addresses in this interface. This approach is required so that the device can be tested and programmed quickly with automated test equipment (ATE) and PROM programmers in the OEM's manufacturing flow. This interface also allows the device to have an efficient programming interface with potentially large future densities, while still fitting into a 32-pin package. Only basic reads, programming, and erase of the nonvolatile memory sectors can be performed through the A/A Mux interface. In this mode FWH features, security features and registers are unavailable. A row/column (R/C) pin determines which set of addresses "rows or columns" are latched.
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Block Diagram
WP TBL FGPI (4:0) ID (3:0) FWH (4:0) CLK INIT OE R/C WE RY/BY A10 - A0 I/O7 - I/O0
RST IC
FWH INTERFACE
FLASH ARRAY
A/A MUX INTERFACE
CONTROL LOGIC
Pin Description
Table 1 details the usage of each of the device pins. Most of the pins have dual functionality, with functions in both the Firmware Hub and A/A Mux interfaces. A/A Mux functionality for pins is shown in bold in the description box for that pin. All pins are designed to be compliant with voltage of VCC + 0.3V max, unless otherwise noted.
Table 1. Pin Description
Interface Symbol IC Type INPUT FWH X A/A Mux X Name and Function INTERFACE CONFIGURATION PIN: This pin determines which interface is operational. This pin is held high to enable the A/A Mux interface. This pin is held low to enable the FWH interface. This pin must be set at power-up or before return from reset and not changed during device operation. This pin is pulled down with an internal resistor, with value between 20 and 100 k. With IC high (A/A Mux mode), this pin will exhibit a leakage current of approximately 200 A. This pin may be floated, which will select FWH mode. INTERFACE RESET: Valid for both A/A Mux and FWH interface operations. When driven low, RST inhibits write operations to provide data protection during power transitions, resets internal automation, and tri-states pins FWH [3:0] (in FWH interface mode). RST high enables normal operation. When exiting from reset, the device defaults to read array mode. PROCESSOR RESET: This is a second reset pin for in-system use. This pin is internally combined with the RST pin. If this pin or RST is driven low, identical operation is exhibited. This signal is designed to be connected to the chipset INIT signal (Max voltage depends on the processor. Do not use 3.3V.) A/A Mux = OE
RST
INPUT
X
X
INIT
INPUT
X
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Table 1. Pin Description (Continued)
Interface Symbol CLK Type INPUT FWH X A/A Mux Name and Function 33 MHz CLOCK for FWH INTERFACE: This input is the same as the PCI clock and adheres to the PCI specification. A/A Mux = R/C FWH I/Os: I/O Communication. A/A Mux = I/O[3:0] FWH INPUT: Input Communication. A/A Mux = WE IDENTIFICATION INPUTS: These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:0] = 0000 and it is recommended that all subsequent devices should use a sequential up-count strapping (i.e., 0001, 0010, 0011, etc.). These pins are pulled down with internal resistors, with values between 20 and 100 k when in FWH mode. Any ID pins that are pulled high will exhibit a leakage current of approximately 200 A. Any pins intended to be low may be left to float. In a single FWH system, all may be left floating. A/A Mux = A[3:0] FWH GENERAL PURPOSE INPUTS: These individual inputs can be used for additional board flexibility. The state of these pins can be read through FWH registers. These inputs should be at their desired state before the start of the PCI clock cycle during which the read is attempted, and should remain at the same level until the end of the read cycle. They may only be used for 3.3V signals. Unused FGPI pins must not be floated. A/A Mux = A[10:6] TOP SECTOR LOCK: When low, prevents programming or sector erase to the highest addressable sector (7 in a 4-Mbit, 15 in an 8-Mbit component) regardless of the state of the lock registers TBL high disables hardware write protection for the top sector, though register-based protection still applies. The status of TBL does not affect the status of sector-locking registers. A/A Mux = A4 WRITE-PROTECT: When low, prevents programming or sector erase to all but the highest addressable sectors (0 - 6 in a 4-Mbit, 0 - 14 in an 8-Mbit component), regardless of the state of the corresponding lock registers. WP-high disables hardware write protection for these sectors, though register-based protection still applies. The status of TBL does not affect the status of sector-locking registers. A/A Mux = A5 X LOW-ORDER ADDRESS INPUTS: Inputs for low-order addresses during read and write operations. Addresses are internally latched during a write cycle. For the A/A Mux interface these addresses are latched by R/C and share the same pins as the high-order address inputs.
FWH[3:0] FWH4 ID[3:0]
I/O INPUT INPUT
X X X
FGPI[4:0]
INPUT
X
TBL
INPUT
X
WP
INPUT
X
A0 - A10
INPUT
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Table 1. Pin Description (Continued)
Interface Symbol I/O0 - I/O7 Type I/O FWH A/A Mux X Name and Function DATA INPUT/OUTPUTS: These pins receive data and commands during write cycles and transmit data during memory array and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. OUTPUT ENABLE: Gates the device's outputs during a read cycle. ROW-COLUMN ADDRESS SELECT: For the A/A Mux interface, this pin determines whether the address pins are pointing to the row addresses, A0 - A10, or to the column addresses, A11 - A18 (AT49LW040) or A11 - A19 (AT49LW080). WRITE ENABLE: Controls writes to the array sectors. Addresses and data are latched on the rising edge of the WE pulse. SECTOR ERASE/PROGRAM POWER SUPPLY: For erasing array sectors or programming data. V PP = 3.3V or 12V. With VPP VPPLK, memory contents cannot be altered. Sector erase or program with an invalid V PP (see DC Characteristics) produces spurious results and should not be attempted. VPP may only be held at 12V for 80 hours over the lifetime of the device. DEVICE POWER SUPPLY: Internal detection automatically configures the device for optimized read performance. Do no float any power pins. With VCC VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltages (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. ANALOG POWER SUPPLY: This supply should share the same system supply as VCC. ANALOG GROUND: Should be tied to same plane as GND. RESERVED FOR FUTURE USE: These pins are reserved for future generations of this product and should be connected accordingly. These pins may be left disconnected or driven. If they are driven, the voltage levels should meet VIH and VIL requirements. A/A Mux = I/O[7:4] X NO CONNECT: Pin may be driven or floated. If it is driven, the voltage levels should meet VIH and VIL. No connects appear only on the 40-lead TSOP package. READY/BUSY: Valid only in A/A Mux Mode. This output pin is a reflection of bit 7 in the status register. This pin is used to determine sector erase or program completion.
OE R/C
INPUT INPUT
X X
WE VPP
INPUT SUPPLY X
X X
VCC
SUPPLY
X
X
GND VCCa GNDa RFU
SUPPLY SUPPLY SUPPLY
X X X X
X X X
NC
X
RY/BY
OUTPUT
X
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Firmware Hub Interface (FWH)
Table 2 lists the seven required signals used for the FWH interface. Table 2. FWH Required Signal List
Direction Signal FWH[3:0] FWH4 RST Peripheral I/O I I Master I/O O I Description Multiplexed command, address and data Indicates start of a new cycle, termination of broken cycle. Reset: Same as PCI Reset on the master. The master does not need this signal if it already has PCIRST on its interface. Clock: Same 33 MHz clock as PCI clock on the master. Same clock phase with typical PCI skew. The master does not need this signal if it already has PCICLK on its interface.
CLK
I
I
FWH[3:0]: The FWH[3:0] signal lines communicate address, control, and data information o ver th e LPC bu s betw een a mas te r an d a p eriph era l. The info rmatio n communicated are: start, stop (abort a cycle), transfer type (memory, I/O, DMA), transfer direction (read/write), address, data, wait states, DMA channel, and bus master grant. FWH4: FWH4 is used by the master to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal is to be used be by peripherals to know when to monitor the bus for a cycle. The FWH4 signal is used as a general notification that the FWH[3:0] lines contain information relative to the start or stop of a cycle, and that peripherals must monitor the bus to determine whether the cycle is intended for them. The benefit to peripherals of FWH4 is, it allows them to enter lower power states internally. When peripherals sample FWH4 active, they are to immediately stop driving the FWH[3:0] signal lines on the next clock and monitor the bus for new cycle information. RESET: RST or INIT at VIL initiates a device reset. In read mode, RST or INIT low deselects the memory, places output drivers in a high-impedance state, and turns off all internal circuits. RST or INIT must be held low for time tPLPH (A/A Mux and FWH operation). The FWH resets to read array mode upon return from reset, and all sectors are set to default (locked) status regardless of their locked state prior to reset. Driving RST or INIT low resets the device, which resets the sector lock registers to their default (write-locked) condition. A reset time (tPHQV A/A Mux) is required from RST or INIT switching high until outputs are valid. Likewise, the device has a wake time (tPHRH A/A Mux) from RST or INIT high until writes to the CUI are recognized. A reset latency will occur if a reset procedure is performed during a programming or erase operation. During sector erase or program, driving RST or INIT low will abort the operation underway, in addition to causing a reset latency. Memory contents being altered are no longer valid, since the data may be partially erased or programmed. It is important to assert RST or INIT during system reset. When the system comes out of reset, it will expect to read from the memory array of the device. If a system reset occurs with no FWH reset (this will be hardware dependent), it is possible that proper CPU initialization will not occur (the FWH memory may be providing status information instead of memory array data).
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C Y C L E T YP E S : T h e r e a r e tw o t y p e s o f c y cl e s t h a t a r e s u p p o r te d b y t h e AT49LW080/040: FWH Memory Read and FWH Memory Write. FWH Memory Read or Write cycles start with a preamble. PREAMBLE: The preamble consists of a START, IDSEL, 28-bit Address and MSIZE fields. The preamble is shown in Figure 1. The preamble begins with FWH4 going low and a START field driven on FWH[3:0]. For FWH Memory Read cycles, the START field must be 1101b; for FWH Memory Write cycles, the START field must be 1110b. Following the START field is the IDSEL field. This field acts like a chip select in that it indicates which device should respond to the current transaction. The next seven clocks are the 28-bit address, which tell from where to begin reading or writing in the selected device. Next, an MSIZE value of 0 indicates the master is requesting a single byte. Figure 1. FWH Memory Cycle Preamble
CLK FWH4 FWH3 - FWH0
START IDSEL 28-BIT ADDRESS MSIZE
START: This one-clock field indicates the start of a cycle. It is valid on the last clock that FWH4 is sampled low. The two start fields that are used for the cycle are shown in Table 3. If the start field that is sampled is not one of these values, then the cycle attempted is not an FWH memory cycle. It may be a valid memory cycle that the FWH component may wish to decode, i.e., it may be of the LPC memory cycle variety. Table 3. Start Fields
FWH[3:0] 1101b 1110b Indication FWH Memory Read FWH Memory Write
IDSEL (DEVICE SELECT): This one-clock field is used to indicate which FWH component is being selected. The four bits transmitted over FWH[3:0] during this clock are compared with values strapped onto pins [ID3:ID0] on the FWH component. If there is a match, the FWH component will continue to decode the cycle to determine which bytes are requested on a read or which bytes to update on a write. If there isn't a match, the FWH component may discard the rest of the cycle and go into a standby power state. MADDR (MEMORY ADDRESS): This is a seven-clock field, which gives a 28-bit memory address. This allows for up to 256 MB per memory device, for a total of a 4 GB addressable space. The address is transferred with the most significant nibble first. MSIZE (MEMORY SIZE): "0000b" will be sent in this field. A value of "0000b" corresponds to a single byte transfer.
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Device Operation
READ: Read operations consist of preamble, TAR, SYNC and data fields as shown in Figure 2 and described in Table 5. TAR and SYNC fields are described below. Commands using the read mode include the following functions: reading memory from the array, reading the identifier codes, reading the lock bit registers and reading the GPI registers. Memory information, identifier codes, or the GPI registers can be read independent of the VPP voltage. Upon initial device power-up or after exit from reset mode, the device automatically resets to read array mode. READ CYCLE, SINGLE BYTE: For read cycles, after the preamble, the master drives a TAR field to give ownership of the bus to the FWH. After the second clock of the TAR phase the FWH assumes the bus and begins driving SYNC values. When it is ready, it drives the low nibble, then the high nibble of data, followed by a TAR field to give control back to the master. Figure 2 shows a device that requires three SYNC clocks to access data. Since the access time can begin once the address phase has been completed, the two clocks of the TAR phase can be considered as part of the access time of the part. For example, a device with a 120 ns access time could assert "0101b" for clocks 1 and 2 of the SYNC phase and "0000b" for the last clock of the SYNC phase. This would be equivalent to five clocks worth of access time if the device started that access at the conclusion of the preamble phase. Once SYNC is achieved, the device then returns the data in two clocks and gives ownership of the bus back to the master with a TAR phase. TURN-AROUND (TAR): This field is two clocks wide, and is driven by the master when it is turning control over to the FWH, (for example, to read data), and is driven by the FWH when it is turning control back over to the master. On the first clock of this two-clock-wide field, the master or FWH drives the FWH[3:0] lines to "1111b". On the second clock of this field, the master or peripheral tri-states the FWH[3:0] lines. SYNC: This field is used to add wait states. It can be several clocks in length. On target or DMA cycles, this field is driven by the FWH. If the FWH needs to assert wait states, it does so by driving "0101b" (short SYNC) on FWH[3:0] until it is ready. When ready, it will drive "0000b". Valid values for this field are shown in Table 4. Table 4. Valid SYNC Values
Bits[3:0] 0000 0101 Indication Ready: SYNC achieved with no error. Short Wait: Part indicating wait states.
Figure 2. FWH Single-byte Read Waveforms
CLK FWH4 FWH[3:0]
START IDSEL MADDR MSIZE TAR SYNC(3) DATA TAR
PREAMBLE
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Table 5. FWH Read Cycle
Clock Cycle 1 Field Name START Field Contents(1) FWH[3:0] 1101b FWH[3:0] Direction IN Comments FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate an FWH memory read cycle. Indicates which FWH device should respond. If the IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to subsequent commands. These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most significant nibble first. The FWH will only support single-byte transfers. In this clock cycle, the master (ICH) has driven the bus to all 1s and then floats the bus, prior to the next clock cycle. This is the first part of the bus "turnaround cycle". The FWH takes control of the bus during this cycle. During the next clock cycle, it will be driving "sync data". The FWH outputs the value 0101, a wait-sync (WSYNC, a.k.a. "short-sync"), for two clock cycles. This value indicates to the master (ICH) that data is not yet available from the part. This number of waitsyncs is a function of the device's access time. During this clock cycle, the FWH will generate a "ready-sync" (RSYNC) indicating that the least significant nibble of the least significant byte will be available during the next clock cycle. YYYY is the least significant nibble of the least significant data byte. YYYY is the most significant nibble of the least significant data byte. The FWH Flash memory drives FWH0 - FWH3 to 1111b to indicate a turnaround cycle. The FWH Flash memory floats its outputs, the master (ICH) takes control of FWH3 - FWH0.
2
IDSEL
0000b to 1111b YYYY
IN
3-9
MADDR
IN
10 11
MSIZE TAR0
0000b (1 byte) 1111b
IN IN then float
12
TAR1
1111b (float)
Float then OUT
13 - 14
WSYNC
0101b (WAIT)
OUT
15
RSYNC
0000b (READY)
OUT
16 17 18 19 Note:
DATA DATA TAR0 TAR1
YYYY YYYY 1111b 1111b (float)
OUT OUT OUT then float Float then IN
1. Field contents are valid on the rising edge of the present clock cycle.
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WRITE: Write operations consist of preamble, data, TAR and SYNC fields as shown in Figure 3 and described in Table 6. WRITE CYCLES, SINGLE BYTE: All devices that support FWH Memory Write cycles must support single-byte writes. FWH Memory Write cycles use the same preamble as FWH Memory Read cycles. For write cycles, after the preamble, the master writes the low nibble, then the high nibble of data. After that the master drives a TAR field to give ownership of the bus to the FWH. After the second clock of the TAR phase, the target device assumes the bus and begins driving SYNC values. A TAR field to give control back to the master follows this. Figure 3. FWH Single-byte Write Waveforms
CLK FWH4 FWH[3:0]
START IDSEL MADDR MSIZE DATA TAR SYNC TAR
PREAMBLE
Table 6. FWH Write Cycle
Field Contents(1) FWH[3:0] 1110b FWH[3:0] Direction IN
Clock Cycle 1
Field Name START
Comments FWH4 must be active (low) for the part to respond. Only the last start field (before FWH4 transitioning high) should be recognized. The START field contents indicate an FWH memory write cycle. Indicates which FWH device should respond. If the IDSEL (ID select) field matches the value ID[3:0], then that particular device will respond to subsequent commands. These seven clock cycles make up the 28-bit memory address. YYYY is one nibble of the entire address. Addresses are transferred most significant nibble first. The FWH only supports single-byte writes. This field is the least significant nibble of the data byte. This data is either the data to be programmed into the Flash memory or any valid Flash command. This field is the most significant nibble of the data byte. In this clock cycle, the master (ICH) has driven the bus to all 1s and then floats the bus prior to the next clock cycle. This is the first part of the bus "turnaround cycle". The FWH takes control of the bus during this cycle. During the next clock cycle it will be driving the "sync" data. The FWH outputs the values 0000, indicating that it has received data or a Flash command. The FWH Flash memory drives FWH0 - FWH 3 to 1111b to indicate a turnaround cycle. The FWH Flash memory floats its outputs, the master (ICH) takes control of FWH3 - FWH0.
2
IDSEL
0000b to 1111b YYYY
IN
3-9
MADDR
IN
10 11
MSIZE DATA
0000b (1 byte) YYYY
IN IN
12 13
DATA TAR0
YYYY 1111b
IN IN then float Float then OUT OUT OUT then Float Float then IN
14 15 16 17 Note:
TAR1 RSYNC TAR0 TAR1
1111b (float) 0000b 1111b 1111b (float)
1. Field contents are valid on the rising edge of the present clock cycle.
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OUTPUT DISABLE: When the FWH is not selected through a FWH read or write cycle, the FWH interface outputs (FWH[3:0]) are disabled and will be placed in a high-impedance state.
Response to Invalid Fields
During FWH operations, the FWH will not explicitly indicate that it has received invalid field sequences. The response to specific invalid fields or sequences is as follows: * Address out of range: The FWH address sequences is seven fields long (28 bits), but only the last five address fields (20 bits) will be decoded by an 8-Mbit FWH. (For a 4-Mbit density, the most significant bit (FWH3) in the third address field also will be ignored.) The FWH will respond to these lower addresses, regardless of the value of the more-significant address bits. Address A22 has the special function of directing reads and writes to the Flash core (A22 = 1) or to the register space (A22 = 0). Invalid MSIZE field: If the FWH receives an invalid size field during a read or write operation, the internal state machine will reset and no operation will be attempted. The FWH will generate no response of any kind in this situation. Invalid-size fields for a read cycle are anything but 0000. Invalid-size fields for a write cycle are anything but 0000. When accessing register space, invalid field sizes are anything but 0000. Once valid START, IDSEL, and MSIZE fields are received, the FWH always will respond to subsequent inputs as if they were valid. As long as the states of FWH [3:0] and FWH4 are known, the response of the FWH to signals received during the FWH cycle should be predictable. The FWH will make no attempt to check the validity of incoming Flash operation commands.
*
Bus Abort
The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4 is driven Low, VIL, during the bus operation; the memory will tri-state the Input/Output Communication pins, FWH3 - FWH0 and the FWH state machine will reset. During a write cycle, there is the possibility that an internal Flash write or erase operation is in progress (or has just been initiated). If the FWH4 is asserted during this time frame, the internal operation will not abort. The software must send an explicit Flash command to terminate or suspend the operation. The internal FWH state machine will not initiate a Flash write or erase operation until it has received the last nibble from the chipset. This means that FWH4 can be asserted as late as cycle 12 (Table 6) and no internal Flash operation will be attempted. HARDWARE WRITE-PROTECT PINS TBL AND WP: Two pins are available with the FWH to provide hardware write-protect capabilities. The Top Sector Lock (TBL) pin is a signal, when held low (active), prevents program or sector erase operations in the top sector of the device (sector 7 - AT49LW040 and sector 15 - AT49LW080) where critical code can be stored. When TBL is high, hardware write protection of the top sector is disabled. The write-protect (WP) pin serves the same function for all the remaining sectors except the top sector. WP operates independently from TBL and does not affect the lock status of the top sector. The TBL and WP pins must be set to the desired protection state prior to starting a program or erase operation since they are sampled at the beginning of the operation. Changing the state of TBL or WP during a program or erase operation may cause unpredictable results.
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If the state of TBL or WP changes during a program suspend or erase suspend state, the changes to the device's locking status do not take place immediately. The suspended operation may be resumed to successfully complete the program or erase operation. The new lock status will take place after the program or erase operation completes. These pins function in combination with the register-based sector locking (to be explained later). These pins, when active, will write-protect the appropriate sector(s), regardless of the associated sector locking registers. (For example, when TBL is active, writing to the top sector is prevented, regardless of the state of the Write Lock bit for the top sector's locking register. In such a case, clearing the write-protect bit in the register will have no functional effect, even though the register may indicate that the sector is no longer locked. The register may still be set to read-lock the sector, if desired.)
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AT49LW080/040
Device Memory Map with FWH Hardware Lock Architecture
AT49LW040
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 Size (Bytes) 64K 64K 64K 64K 64K 64K 64K 64K Address Range 00000 - 0FFFF 10000 - 1FFFF 20000 - 2FFFF 30000 - 3FFFF 40000 - 4FFFF 50000 - 5FFFF 60000 - 6FFFF 70000 - 7FFFF Hardware Write-protect Pin WP WP WP WP WP WP WP TBL
AT49LW080
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 Size (Bytes) 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K Address Range 00000 - 0FFFF 10000 - 1FFFF 20000 - 2FFFF 30000 - 3FFFF 40000 - 4FFFF 50000 - 5FFFF 60000 - 6FFFF 70000 - 7FFFF 80000 - 8FFFF 90000 - 9FFFF A0000 - AFFFF B0000 - BFFFF C0000 - CFFFF D0000 - DFFFF E0000 - EFFFF F0000 - FFFFF Hardware Write-protect Pin WP WP WP WP WP WP WP WP WP WP WP WP WP WP WP TBL
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Register-based Locking and Generalpurpose Input Registers
A series of registers are available in the FWH to provide software read and write locking and GPI feedback. These registers are accessible through standard addressable memory space. REGISTERS: The AT49LW040/080 has two types of registers: sector-locking registers and general-purpose input registers. The two types of registers appear at their respective address locations in the 4 GB system memory map. SECTOR-LOCKING REGISTERS: The AT49LW040 and the AT49LW080 have 8 (LR0 - LR7) and 16 (LR0 - LR15) sector-locking registers, respectively. Each sector-locking register controls the lock protection for 64K bytes of memory as shown in Table 7 (AT49LW040) and Table 8 (AT49LW080). The sector-locking registers are accessible through the register memory address shown in the third column of Table 7 and Table 8. The sector-locking registers are read/write as shown in the last column of Table 7 and Table 8. Each sector has three dedicated locking bits as shown in Table 9 and Table 10.
Table 7. Sector-locking Registers for AT49LW040
Register Name LR0 LR1 LR2 LR3 LR4 LR5 LR6 LR7 FGPI-REG Sector Size 64K 64K 64K 64K 64K 64K 64K 64K Register Memory Address FFB80002H FFB90002H FFBA0002H FFBB0002H FFBC0002H FFBD0002H FFBE0002H FFBF0002H FFBC0100H Default Value 01H 01H 01H 01H 01H 01H 01H 01H N/A Type R/W R/W R/W R/W R/W R/W R/W R/W RO
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AT49LW080/040
Table 8. Sector-locking Registers for AT49LW080
Register Name LR0 LR1 LR2 LR3 LR4 LR5 LR6 LR7 LR8 LR9 LR10 LR11 LR12 LR13 LR14 LR15 FGPI-REG Sector Size 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K 64K Register Memory Address FFB00002H FFB10002H FFB20002H FFB30002H FFB40002H FFB50002H FFB60002H FFB70002H FFB80002H FFB90002H FFBA0002H FFBB0002H FFBC0002H FFBD0002H FFBE0002H FFBF0002H FFBC0100H Default Value 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H 01H N/A Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO
Table 9. Function of Sector-locking Bits
Bit 7:3 2 Function Reserved Read Lock 1 = Prevents read operations in the sector where set. 0 = Normal operation for reads in the sector where clear. This is the default state. Lock-down 1 = Prevents further set or clear operations to the Write Lock and Read Lock bits. Lock-down can only be set, but not cleared. The sector will remain locked-down until reset (with RST or INIT), or until the device is power-cycled. 0 = Normal operation for Write Lock and Read Lock bits altering in the sector where clear. This is the default state. Write Lock 1 = Prevents program or erase operations in the sector where set. This is the default state. 0 = Normal operation for programming and erase in the sector where clear.
1
0
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Table 10. Register-based Locking Value Definitions
Data 00 01 02 03 04 05 06 07 Note: Reserved Data 7 - 3 00000 00000 00000 00000 00000 00000 00000 00000 Read Lock, Data 2 0 0 0 0 1 1 1 1 Lock-down, Data 1 0 0 1 1 0 0 1 1 Write Lock, Data 0 0 1 0 1 0 1 0 1 Resulting Sector State(1) Full access Write locked. Default state at power-up Locked open (full access locked down) Write locked down Read locked Read and write locked Read locked down Read and write locked down
1. The Write Lock bit must be set to the desired protection state prior to starting a program or erase operation since it is sampled at the beginning of the operation. Changing the state of the Write Lock bit during a program or erase operation may cause unpredictable results. If the state of the Write Lock bit changes during a program suspend or erase suspend state, the changes to the sector's locking status do not take place immediately. The suspended operation may be resumed successfully. The new lock status will take place after the program or erase operation completes. The individual bit functions are described in the following sections.
READ LOCK: The default read status of all sectors upon power-up is read-unlocked. When a sector's read-lock bit is set (1 state), data cannot be read from that sector. An attempted read from a read-locked sector will result in data 00H being read. (Note that failure is not reflected in the status register). The read-lock status can be unlocked by clearing (0 state) the read-lock bit, provided the lock-down bit has not been set. The current read-lock status of a particular sector can be determined by reading the corresponding read-lock bit. WRITE LOCK: The default write status of all sectors upon power-up is write-locked (1 state). Any program or erase operations attempted on a locked sector will return an error in the status register (indicating sector lock). The status of the locked sector can be changed to unlocked (0 state) by clearing the write-lock bit, provided the lock-down bit is not also set. The current write-lock status of a particular sector can be determined by reading the corresponding write-lock bit. Any program or erase operations attempted on a locked sector will return an error in the status register (indicating sector lock). The write-lock functions in conjunction with the hardware write-lock pins, TBL and WP. When active, these pins take precedence over the register-locking function and writelock the top sector or remaining sectors, respectively. Reading this register will not read the state of the TBL or WP pins. LOCK-DOWN: When in the FWH interface mode, the default lock-down status of all sectors upon power-up is not-locked-down (0 state). The lock-down bit for any sector may be set (1 state), but only once, as future attempted changes to that sector locking register will be ignored. The lock-down bit is only cleared upon a device reset with RST or INIT. The current lock-down status of a particular sector can be determined by reading the corresponding lock-down bit. Once a sector's lock-down bit is set, the read- and write-lock bits for that sector can no longer be modified and the sector is locked down in its current state of read and write accessibility. GENERAL-PURPOSE INPUTS REGISTER: This register reads the status of the FGPI[4:0] pins on the FWH at power-up. Since this is a pass-through register, there is no default value as shown in Table 7 and Table 8. It is recommended that the GPI pins be in the desired state before FWH4 is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle.
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AT49LW080/040
Table 11. General-purpose Input Registers
Bit 7:5 4 3 2 1 0 Function Reserved FGPI[4] Reads status of general-purpose input pin (PLCC-30/TSOP-7) FGPI[3] Reads status of general-purpose input pin (PLCC-3/TSOP-15) FGPI[2] Reads status of general-purpose input pin (PLCC-4/TSOP-16) FGPI[1] Reads status of general-purpose input pin (PLCC-5/TSOP-17) FGPI[0] Reads status of general-purpose input pin (PLCC-6/TSOP-18)
Command Definitions in (Hex)
1st Bus Cycle Command Sequence Read Array/Reset Sector Erase
(2)(3) (2)(4)
2nd Bus Cycle Operation Addr Data
Bus Cycles 1 2 2 1
Operation Write Write Write Write
Addr XXXX SA Addr XXXX
Data FF 20 40 or 10 B0
Write Write
SA Addr
D0 DIN
Byte Program
Sector Erase Suspend(2) Program Suspend
(2)
Write Write 1 Write 2 2 1 Write Write Write XXXX XXXX XXXX 90 70 50 Read Read AID(6) XXXX DOUT SRD(7) XXXX D0
Sector Erase Resume(2) Program Resume
(2)
Product ID Entry(5) Read Status Register Clear Status Register Notes:
1. X = Any valid address within the device 2. The sector must be not be write locked when attempting sector erase or program operations. Attempts to issue a sector erase or byte program to a write locked sector will fail. 3. SA = Sector address. Any byte address within a sector can be used to designate the sector address (see page 13). 4. Either 40H or 10H is recognized as the program setup. 5. Following the Product ID Entry command, read operations access manufacture and device ID. See Table 12. 6. AID = Address used to read data for manufacture or device ID 7. SRD = Data Read from status register
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READ ARRAY: Upon initial device power-up and after exit from reset, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal state machine (WSM) has started a block erase or program operation, the device will not recognize the Read Array Command until the operation is completed, unless the operation is suspended via an Erase Suspend or Program Suspend Command. The Read Array command functions independently of the VPP voltage. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. Following the Product ID Entry command, read cycles from the addresses shown in Table 12 retrieve the manufacturer and device code. To exit the product identification mode, any valid command can be written to the device. The Product ID Entry command functions independently of the VPP voltage. Table 12. Identifier Codes
Code Manufacturer Code AT49LW040 Device Code AT49LW080 000001 E1 Address (AID) 000000 000001 Data 1F E0
SECTOR ERASE: Before a byte can be programmed, it must be erased. The erased state of the memory bits is a logical "1". Since the AT49LW080/040 does not offer a complete chip erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second falling edge of the WE will be erased, provided the given sector is not protected. Successful sector erase requires that the corresponding sector's Write Lock bit be cleared and the corresponding write-protect pin (TBL or WP) be inactive. If sector erase is attempted when the sector is locked, the sector erase will fail, with the reason for failure in the status register. Successful sector erase only occurs when VPP = VPPH1 or VPPH2. If the erase operation is attempted at VPP VPPH1 or VPPH2 erratic results may occur. BYTE PROGRAMMING: The device is programmed on a byte-by-byte basis. Programming is accomplished via the internal device command register and is a two-bus cycle operation. The programming address and data are latched in the second bus cycle. The device will automatically generate the required internal programming pulses. Please note that a "0" cannot be programmed back to a "1"; only an erase operation can convert "0"s to "1"s. After the program command is written, the device automatically outputs the status register data when read. When programming is complete, the status register may be checked. If a program error is detected, the status register should be cleared before corrective action is taken by the software. The internal WSM verification Error Checking only detects "1"s that do not successfully program to "0"s. Reliable programming only occurs when VPP = VPPH1 or VPPH2. If the program operation is attempted at VPP VPPH1 or VPPH2 erratic results may occur. A successful program operation also requires that the corresponding sector's Write Lock bit be cleared, and the corresponding write-protect pin (TBL or WP) be inactive. If a program operation is attempted when the sector is locked, the operation will fail.
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AT49LW080/040
ERASE SUSPEND: The Erase Suspend command allows sector-erase interruption to read or program data in another sector of memory. Once the sector erase process starts, writing the sector erase suspend command requests that the WSM suspend the sector erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the sector erase suspend command is written. Polling the status register can help determine when the sector erase operation was suspended. After a successful suspend, a Read Array command can be written to read data from a sector other than the suspended sector. A program command sequence may also be issued during erase suspend to program data in sectors other than the sector currently in the erase suspend mode. The other valid commands while sector erase is suspended include Read Status Register and Sector Erase Resume. After a Sector Erase Resume command is written, the WSM will continue the sector erase process. VPP must remain at VPPH1/2 (the same VPP level initially used for sector erase) while sector erase is suspended. RST or INIT must also remain at VIH. Sector erase cannot resume until program operations initiated during sector erase suspend have completed. PROGRAM SUSPEND: The Program Suspend command allows program interruption to read data in other memory locations. Once the program process starts, writing the Program Suspend Command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the program suspend command is written. Polling the status register can help determine when the program operation was suspended. After a successful suspend, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while program is suspended are Read Status Register and Program Resume. VPP must remain at VPPH1/2 (the same VPP level used for program) while in program suspend mode. RST or INIT must also remain at VIH. READ STATUS REGISTER: The status register may be read to determine when a sector erase or program completes and whether the operation completed successfully. The status register may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations will return data from the status register until another valid command is written. The Read Status Register command functions independently of the VPP voltage. CLEAR STATUS REGISTER: Error flags in the status register can only be set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions. The Clear Status Register command functions independently of the applied VPP voltage.
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Status Register Definition
B7 Write State Machine Status(1) 1 0 1 B6 Erase Suspend Status 0 B5 Erase Status(2) 1 0 1 B4 Program Status 0 B3 VPP Status(3) 1 0 1 B2 Program Suspend Status 0 B1 B0 Notes: Device Protect Status(4) Reserved for Future Enhancements
(5)
Ready Busy Sector Erase Suspended Sector Erase in Progress/Completed Error in Sector Erasure Successful Sector Erase Error in Program Successful Program VPP Low Detect, Operation Abort VPP OK Program Suspended Program in Progress/Completed Write Lock Bit, TBL Pin or WP Pin Detected, Operation Abort Unlock
1 0
1. Check B7 to determine sector erase or program completion. B6 - B0 are invalid while B7 = "0". 2. If both B5 and B4 are "1"s after a sector erase attempt, an improper command sequence was entered. 3. B3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after a sector erase or program operation. B3 is not guaranteed to report accurate feedback only when VPP VPPH1/2. 4. B1 does not provide a continuous indication of Write Lock bit, TBL pin or WP pin values. The WSM interrogates the Write Lock bit, TBL pin or WP pin only after a sector erase or program operation. Depending on the attempted operation, it informs the system whether or not the selected sector is locked. 5. B0 is reserved for future use and should be masked out when polling the status register.
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AT49LW080/040
A/A Mux Interface
The following information applies only to the AT49LW040/080 when in A/A Mux Mode. Information on FWH Mode (the standard operating mode) is detailed earlier in this document. Electrical characteristics in A/A Mux Mode are provided on pages starting from page 27. The AT49LW040/080 is designed to offer a parallel programming mode for faster factory programming. This mode, called A/A Mux Mode, is selected by having this IC pin high. The IC pin is pulled down internally in the AT49LW040/080, so a modest current should be expected to be drawn (see Table 1 on page 3 for further information). Four control pins dictate data flow in and out of the component: R/C, OE, WE, and RST. R/C is the A/A Mux control pin used to latch row and column addresses. OE is the data output control pin (I/O0 - I/O7), drives the selected memory data onto the I/O bus, when active WE and RST must be at VIH. BUS OPERATION: All A/A Mux bus cycles can be conformed to operate on most automated test equipment and PROM programmers.
Bus Operations
Mode Read
(1)(2)(6)
RST VIH VIH VIH VIH
OE VIL VIH VIL VIH
WE VIH VIH VIH VIL
Address X X
(3)
VPP X X X X
I/O0 - I/O7 DOUT High-Z Note 3 DIN
Output Disable(6) Product ID Entry(6) Write Notes:
(4)(5)(6)
X
1. When VPP V PPLK, the memory contents can be read, but not altered. 2. X can be VIL or VIH for control and address input pins and VPPLK or V PPH1/2 for the VPP supply pin. See the "DC Characteristics" for VPPLK and VPPH1/2 voltages. 3. See Table 12 on page 18 for Product ID Entry data and addresses. 4. Command writes involving sector erase or program are reliably executed when V PP = VPPH1/2 and VCC = VCC 0.3V. 5. Refer to "A/A Mux Read-only Operations" for valid DIN during a write operation. 6. VIH and VIL refer to the DC characteristics associated with Flash memory output buffers: VIL min = 0.5V, VIL max = 0.8V, VIH min = 2.0V, VIH max = VCC + 0.5V.
OUTPUT DISABLE/ENABLE: With OE at a logic-high level (VIH), the device outputs are disabled. Output pins I/O0 - I/O7 are placed in the high-impedance state. With OE at a logic-low level (VIL), the device outputs are enabled. Output pins I/O0 - I/O7 are placed in a output-drive state. ROW/COLUMN ADDRESSES: R/C is the A/A Mux control pin used to latch row (A0 A10) and column addresses (A11 - A18) [AT49LW040], or (A11 - A19) [AT49LW080]. R/C latches row addresses on the falling edge and column addresses on the rising edge. RDY/BUSY: An open drain Ready/Busy output pin provides a hardware method of detecting the end of a program or erase operation. RDY/Busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle.
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Absolute Maximum Ratings*
Voltage on Any Pin (except VPP) .................................-0.5V to +VCC + 0.5V(1)(2)(4) VPP Voltage ............................................ -0.5V to +13.0V(1)(2)(3) *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Notes:
1. All specified voltages are with respect to GND. Minimum DC voltage on the VPP pin is -0.5V. During transitions, this level may undershoot to -2.0V for periods of <20 ns. During transitions, this level may overshoot to VCC + 2.0V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +13.0V for periods <20 ns. 3. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours. 4. Do not violate processor or chipset limitations on the INIT pin.
Operating Conditions
Temperature and VCC
Symbol TC VCC Note: Parameter Operating Temperature
(1)
Test Condition Case Temperature
Min 0 3.0
Max +85 3.6
Unit C V
VCC Supply Voltage (3.3V 0.3V)
1. This temperature requirement is different from the normal commercial operating condition of Flash memories.
FWH Interface DC Input/Output Specifications
Symbol VIH(3) VIH (INIT) VIL (INIT) VIL
(3) (5)
Parameter Input High Voltage INIT Input High Voltage INIT Input Low Voltage Input Low Voltage Input Leakage Current(1) Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance Recommended Pin Inductance
Conditions
Min 0.5 VCC 1.35
Max VCC + 0.5 VCC + 0.5 0.85
Units V V V V A V
(5)
-0.5 0 < VIN < VCC IOUT = -500 A IOUT = 1500 A 0.9 VCC
0.3 VCC 10
IIL(4) VOH VOL CIN CCLK L
pin(2)
0.1 VCC 13 3 12 20
V pF pF nH
Notes:
1. 2. 3. 4. 5.
Input leakage currents include high-Z output leakage for all bi-directional buffers with tri-state outputs. Refer to PCI spec. Inputs are not "5-volt safe." IIL may be changed on IC and ID pins (up to 200 A) if pulled against internal pull-downs. Refer to the pin descriptions Do not violate processor or chipset specifications regarding the INIT pin voltage.
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AT49LW080/040
Power Supply Specifications - All Interfaces
Symbol VPPH1 VPPH2 VPPLK VLKO ICCSL1 Parameter VPP Voltage VPP Voltage VPP Lockout Voltage VCC Lockout Voltage VCC Standby Current (FWH Interface)
(2)
Conditions
Min 3.0 11.4 1.5 1.5
Max 3.6 12.6
Units V V V V
Voltage range of all inputs is VIH to VIL, FWH4 = V IH,(3) VCC = 3.6V, CLK f = 33 MHz No internal operations in progress
100
(4)
A
ICCSL2
VCC Standby Current (FWH Interface)(2)
FWH4 = VIL(3) VCC = 3.6V, CLK f = 33 MHz No internal operations in progress
10(4)
mA
ICCA
VCC Active Current(2)
VCC = VCC Max,(3) CLK f = 33 MHz Any internal operation in progress, IOUT = 0 mA
67(4)
mA
IPPR IPPWE Notes: 1. 2. 3. 4.
VPP Read Current
(2)
VPP VCC VPP = 3.0 - 3.6V
(2) (2)
200 40 15
A mA mA
VPP Program or Erase Current
VPP = 11.4 - 12.6V
All currents are in RMS unless otherwise noted. These currents are valid for all packages. VPP = VCC. VIH = 0.9 VCC, VIL = 0.1 VCC per the PCI output VOH and VOL spec. This number is the worst case of IPP + ICC Memory Core + ICC FWH Interface.
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FWH Interface AC Input/Output Specifications
Symbol Ioh(AC) Parameter Switching Current High Condition 0 < VOUT 0.3 V CC 0.3 VCC < VOUT <0.9 VCC 0.7 VCC < VOUT < VCC (Test Point) Iol(AC) Switching Current Low VOUT = 0.7 VCC VCC > VOUT 0.6 VCC 0.6 VCC > VOUT > 0.1 VCC 0.18 VCC > VOUT > 0 (Test Point) Icl Ich slewr slewf Notes: Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.18 VCC -3 < VIN -1 VCC + 4 > VIN V CC + 1 0.2 VCC - 0.6 VCC load(1) 0.6 VCC - 0.2 VCC load
(1)
Min -12 V CC -17.1 (VCC - VOUT)
Max
Units mA mA
Note 2 -32 VCC 16 VCC -17.1 (VCC - VOUT) Note 3 38 VCC -25 + (VIN + 1)/0.015 25 + (VIN - V CC - 1)/0.015 1 1 4 4 mA mA mA V/ns V/ns mA mA mA
1. PCI specification output load is used. 2. IOH = (98.0/VCC ) * (VOUT - VCC) *(VOUT + 0.4 VCC). 3. IOL = (256/VCC) * VOUT (VCC - VOUT).
FWH Interface AC Timing Specifications Clock Specification
Symbol tCYC tHIGH tLOW Notes: Parameter CLK Cycle Time(1) CLK High Time CLK Low Time CLK Slew Rate RST or INIT Slew Rate(2) peak-to-peak Condition Min 30 11 11 1 50 4 Max Units ns ns ns V/ns mV/ns
1. PCI components must work with any clock frequency between nominal DC and 33 MHz. Frequencies less than16 MHz may be guaranteed by design rather than testing. 2. Applies only to rising edge of signal.
Clock Waveform
tCYC tHIGH 0.6 VCC 0.5 VCC 0.4 VCC 0.3 VCC 0.2 VCC tLOW 0.4 VCC, p-to-p (minimum)
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Signal Timing Parameters
Symbol tCHQX tCHQX tCHQZ tAVCH tDVCH tCHAX tCHDX tVSPL tCSPL tPLQZ Notes: PCI Symbol tval ton toff tsu th trst trst-clk trst-off Parameter CLK to Data Out(1) CLK to Active (Float to Active Delay)(2) CLK to Inactive (Active to Float Delay) Input Set-up Time Input Hold Time(3) Reset Active Time after Power Stable Reset Active Time after CLK Stable Reset Active to Output Float Delay
(2) (3) (2)
Min 2 2
Max 11
Units ns ns
28 7 0 1 100 48
ns ns ns ms s ns
1. Minimum and maximum times have different loads. See PCI spec. 2. For purposes of Active/Float timing measurements, the high-Z or "off" state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 3. This parameter applies to any input type (excluding CLK).
Output Timing Parameters
CLK Vth Vtl
Vtest tval
FWH[3:0] (Valid Output Data)
FWH[3:0] (Float Output Data) ton toff
Input Timing Parameters
CLK tsu FWH[3:0] (Valid Input Data) Inputs Valid Vth Vtl th Vmax
Vtest
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1966C-FLASH-03/02
Interface Measurement Condition Parameters
Symbol Vth(1) Vtl(1) Vtest Vmax(1) Input Signal Edge Rate Note: Value 0.6 V CC 0.2 V CC 0.4 V CC 0.4 V CC 1 V/ns Units V V V V
1. The input test environment is done with 0.1 VCC of overdrive over VIH and VIL. Timing parameters must be met with no more overdrive than this. Vmax specifies the maximum peak-to-peak waveform allowed for measuring the input timing. Production testing may use different voltage values, but must correlate results back to these parameters.
Reset Operations
Symbol tPLPH(1) Note: Parameter RST or INIT Pulse Low Time (If RST or INIT is tied to VCC, this specification is not applicable) Min 100 Max Unit ns
1. A reset latency of 20 s will occur if a reset procedure is performed during a programming or erase operation.
AC Waveform for Reset Operation
RST VIH VIL tPLPH
Sector Programming Times
3.3V VPP Parameter Byte Program Time(2) Sector Program Time Sector Erase Time Notes:
(2) (2)
12V VPP Max 300 20.0 1.0 Typ
(1)
Typ
(1)
Max 125 8.0 0.5
Unit s sec sec
30.0 2.0 0.8
12.0 0.8 0.35
1. Typical values measured at TA = +25C and nominal voltages. 2. Excludes system-level overhead.
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ELECTRICAL CHARACTERISTICS IN A/A MUX MODE: Certain specifications differ from the previous sections, when programming in A/A Mux Mode. The following subsections provide this data. Any information that is not shown here is not specific to A/A Mux Mode and uses the FWH Mode specifications. When the VPP voltage is VPPLK, read operations from memory or reading the Product ID are enabled, but programming and erase functions are disabled. Placing VPPH1/2 on VPP enables successful sector erase and program operations.
A/A Mux Mode Interface DC Input/Output Specifications
Symbol VIH VIL
(3)
Parameter Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance Recommended Pin Inductance
Conditions
Min 0.5 VCC -0.5
Max VCC + 0.5 0.8 +10
Unit V V A V V
(3)
IIL(4) VOH VOL CIN CCLK LPIN
(2)
VCC = VCC max, Vout = VCC or GND VCC = VCC min, IOH = -2.5 mA VCC = VCC min, IOH = -100 A VCC = VCC min, IOL = 2 mA 0.85 VCC Min VCC = 0.4
0.4 13 3 12 20
V pF pF nH
Notes:
1. 2. 3. 4.
Input leakage currents include high-Z output leakage for all bi-directional buffers with tri-state outputs. Refer to PCI spec. Inputs are not "5-volt safe." IIL may be changed on IC and ID pins (up to 200 A) if pulled against internal pull-downs. Refer to the pin descriptions.
Reset Operations
Symbol tPLPH tPLRH Notes: Parameter RST Pulse Low Time (If RST is tied to VCC, this specification is not applicable.) RST Low to Reset during Sector Erase or Program(1)(2) 1. If RST is asserted when the WSM is not busy (RY/BY = 1), the reset will complete within 100 ns. 2. A reset time, tPHAV, is required from the latter of RY/BY or RST going high until outputs are valid. Min 100 20 Max Unit ns s
AC Waveforms for Reset Operations
RY/BY VIH VIL tPLRH RST VIH VIL tPLPH
27
1966C-FLASH-03/02
A/A Mux Read-only Operations(1)(2)
Symbol tAVAV tAVCL tCLAX tAVCH tCHAX tCHQV tGLQV tPHAV tGLQX tGHQZ tQXGH Note: Parameter Read Cycle Time Row Address Setup to R/C Low Row Address Hold from R/C Low Column Address Setup to R/C High Column Address Hold from R/C High R/C High to Output Delay OE Low to Output Delay
(2)
Min 250 50 50 50 50
Max
Units ns ns ns ns ns
150 50 1 0 50 0
ns ns s ns ns ns
(2)
RST High to Row Address Setup OE Low to Output in Low-Z OE High to Output in High-Z Output Hold from OE High 1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE may be delayed up to tCHQV - tGLQV after the rising edge of R/C without impact on tCHQV. 3. TC = 0C to +85C, 3.3V + 0.3V VCC.
A/A Mux Read Timing Diagram
tAVAV ADDRESSES VIH VIL
Row Address Stable Column Address Stable Next Address Stable
tAVCL
tCLAX tAVCH
tCHAX tCHQV tGLQV tGHQZ
VIH R/C VIL
OE
VIH VIL tPHAV
High-Z Data Valid
tQXGH
High-Z
I/O
VOH VOL
tGLQX
WE
VIH VIL
RST
VIH VIL
28
AT49LW080/040
1966C-FLASH-03/02
AT49LW080/040
A/A Mux Write Operations(1)(2)
Symbol tPHWL tWLWH tDVWH tWHDX tAVCL tCLAX tAVCH tCHAX tWHWL tCHWH tVPWH tWHGL tWHRL tQVVL Notes: Parameter RP High Recovery to WE Low Write Pulse Width Low Data Setup to WE High(1) Data Hold from WE High
(1) (1) (1)
Min 1 100 50 5 50 50 50 50 100 50 100
Max
Units s ns ns ns ns ns ns ns ns ns ns
Row Address Setup to R/C Low
Row Address Hold from R/C Low
Column Address Setup to R/C High(1) Column Address Hold from R/C High(1) Write Pulse Width High R/C High Setup to WE High VPP1,2 Setup to WE High Write Recovery before Read WE High to RY/BY Going Low VPP1,2 Hold from Valid SRD, RY/BY High
150 0 0
ns ns ns
1. Refer to "A/A Mux Read-only Operations" for valid AIN and DIN for sector erase or program, or other commands. 2. TC = 0C to +85C, 3.3V 0.3V VCC.
29
1966C-FLASH-03/02
A/A Mux Write Timing Diagram

VIH ADDRESSES VIL
R1
C1
R2
C2
tAVCL tCLAX
tAVCH tCHAX
VIH R/C VIL tPHWL WE VIH VIL
tWHWL tWLWH
tCHWH
tWHGL OE VIH VIL tDVWH DIN DIN tWHRL
Valid SRD
tWHDX
I/O
VOH VOL
RY/BY
VIH VIL
RST
VIH VIL
t tVPWH tQVVL
VPP (V)
VPPH1,2 VIL
NOTES A = VCC power-up and standby B = Write sector erase or program setup C = Write sector erase confirm or valid address and data D = Automated erase or program delay E = Read status register data F = Ready to write another command
30
AT49LW080/040
1966C-FLASH-03/02

A
B
C
D
E
F
AT49LW080/040
AT49LW040 Ordering Information
ICC (mA) Active 67 Standby 0.10 Ordering Code AT49LW040-33JC AT49LW040-33TC Package 32J 40T Operation Range Extended Commercial (0 to 85C)
AT49LW080 Ordering Information
ICC (mA) Active 67 Standby 0.10 Ordering Code AT49LW080-33JC AT49LW080-33TC Package 32J 40T Operation Range Extended Commercial (0 to 85C)
Package Type 32J 40T 32-lead, Plastic J-leaded Chip Carrier Package (PLCC) 40-lead, Thin Small Outline Package (TSOP)
31
1966C-FLASH-03/02
Packaging Information
32J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL
D2
MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330
NOM - - - - - - - - - - - 1.270 TYP
MAX 3.556 2.413 - 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533
NOTE
A A1 A2 D D1 D2
Note 2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum.
E E1 E2 B B1 e
Note 2
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B
R
32
AT49LW080/040
1966C-FLASH-03/02
AT49LW080/040
40T - TSOP
PIN 1
0 ~ 8
c
Pin 1 Identifier D1 D
L
e
b
L1
E
A2
A
SEATING PLANE
GAGE PLANE
A1
SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation CD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.05 0.95 19.80 18.30 9.90 0.50 NOM - - 1.00 20.00 18.40 10.00 0.60 0.25 BASIC 0.17 0.10 0.22 - 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 10.10 0.70 Note 2 Note 2 NOTE
10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40T, 40-lead (10 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 40T REV. B
R
33
1966C-FLASH-03/02
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
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1966C-FLASH-03/02 /xM

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